The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type, stack gate type or a combination thereof. The present invention also relates to a semiconductor memory array of floating gate memory cells of the forgoing types.
Non-volatile semiconductor memory cell using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the scale of integration of semiconductor processing increases, reducing the largest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
In the present invention, three self-aligned methods are disclosed to form semiconductor memory arrays of floating gate memory cells of the split gate type, stacked gate type, and a combination thereof, as well as such memory arrays formed thereby. In the self aligned method of forming a semiconductor memory array of floating gate memory cells of the split gate type, the memory cell has a first terminal, a second terminal with a channel between the first terminal and the second terminal, a floating gate, and a control gate. In the method, a plurality of spaced apart isolation regions are formed in the substrate. The isolation regions are substantially parallel to one another in a first direction with an active region between each pair of adjacent isolation regions. Each active region has a first layer of insulating material on the semiconductor substrate, and a first layer of polysilicon material on the first layer of insulating material. A plurality of spaced apart masking regions of a masking material are formed substantially parallel to one another on said semiconductor substrate in a second direction crossing a plurality of alternating active regions and isolation regions. The second direction is substantially perpendicular to the first direction. Etching along the second direction under the masking material is then performed. A plurality of spaced apart first spacers of an insulating material are formed substantially parallel to one another in the second direction. Each of the first spacers is adjacent to and contiguous with one of the masking regions with a first region between each pair of adjacent first spacers. Each first spacer crossing a plurality of alternating active regions and isolation regions. Between each pair of adjacent first spacers in the first region, the material is etched. A first terminal is formed in the substrate in the active region between pairs of adjacent first spacers in the first region. A conductor is formed in the second direction between each pair of spaced apart first spacers, electrically connected to the first terminal in the substrate. The masking material is removed resulting in a plurality of spaced apart structures substantially parallel to one another in the second direction. An insulating film is formed about each of these structures. A plurality of spaced apart second spacers of polysilicon material substantially parallel to one another is formed in the second direction. Each second spacer is adjacent to and contiguous with one of the structures. A second region is between each pair of adjacent second spacers with each second spacer crossing a plurality of alternating active regions and isolation regions. Each of the second spacer electrically connects the control gates for the memory cells in the second direction. Between each pair of adjacent second spacers in the second region, the material is etched. A second terminal is formed in the substrate in each of the active regions between pairs of adjacent second spacers in the second region. Finally, a conductor is formed in a first direction substantially parallel to an active region and electrically connected to the second terminals in the first direction.
A semiconductor memory array of a floating gate memory cell of the split gate type is formed by the foregoing method.